Abstract:
A behavioral model of the modular reduction device with optimal hardware costs was designed in
CAD Quartus Prime Lite Edition. An algorithm of operation is implemented in the Verilog HDL
language. A method is used where, at each step of the calculation, the value of either tripled, doubled,
or single value of the module is subtracted from the most significant bits shifted to the left by two.
Functional and timing modeling of the behavioral model algorithm using examples was carried out and
the correctness of the algorithm was confirmed. The device circuit at the register transfer level (RTL)
for the low-budget FPGA Cyclone VE 5CEBA4F23C7 from Altera is obtained. A timing analysis was
performed using a time analyzer to determine the maximum clock frequency for the principal and
behavioral models in various working conditions.
